- The Synopsys VCS® functional verification solution is the primary verification solution used by a majority of the world’s top 20 semiconductor companies. VCS provides the industry’s highest performance simulation and constraint solver engines.
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Using Synopsys VCS. You will also learn how to use the GTKWave Waveform Viewer to visualize the various signals in your simulated RTL designs. Figure 1 illustrates the basic VCS tool ow and how it ts into the larger ECE5745 ow. VCS takes a set of Verilog les as input and produces an executable simulator as an output.
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graphical user interface (GUI) or a text script. For information about
downloading Synopsys Installer and VCS MX, see “Downloading the
Software” in Installing Synopsys Tools
To install VCS MX by EST or from the CD, follow the procedures
described in Installing Synopsys Tools
Example 1-1 in Installing Synopsys Tools shows a Synopsys media
installation script for the synthesis tools. VCS MX is installed in a similar
manner.
VCS MX is a stand-alone product and cannot be installed over an existing
Synopsys product, including a prior version of VCS MX. You must create
a new directory for VCS MX.
Follow these steps.
1. Set the VCS_HOME environment variable in the shell that you are using
in which the root_directory argument is the name of the
VCS MX root directory.
- If you are using the C shell, enter
% setenv VCS_HOME /vcs_mx/build/vcs_mx/vcs_mxC-2009.06
- If you are using the Bourne shell, enter
% VCS_HOME=/vcs_mx/build/vcs_mx/vcs_mxC-2009.06
export VCS_HOME
2. Add the directory containing the VCS MX executable files to the PATH
environment variable.
- If you are using the C shell, add the following line to the .cshrc file:
set path=($VCS_HOME/bin $path)
- If you are using the Bourne, Korn, or Bash shell, add the following
line to the .profile or .kshrc file:
PATH=(path:$VCS_HOME/bin)
export PATH
1, VCs commonly used compile command:
VCs source_files [source_or_object_files] Options
e.g VCs TOP.V toil.v-ri +v2k
Details of Options:
-I: Compiles for interactive use
+v2k:enables New language features in the proposed IEEE 1364-2001 standard. See 'Implemented IEEE STD 1364-2001 Language constructs' on page 2-23.
- R after compilation, run simulation executable
-ri After compilation, run simulation under Xvcs
-sverilog
Enables the use of the Verilog language extensions in the Accellera
SystemVerilog specification.
-debug
Enables the use of UCLI commands and DVE.
-debug_all
Enables the use of UCLI and DVE. Also enables line stepping.
-doc
Starts browser to display the HTML files for the VCS/VCSI documentation.
-VCD <filename>
Sets the output VCD file name to the specified file.
The default filename is verilog.dump.
A $dumpfile System Task in the Verilog source code would override
This option.
+vcdfile+<filename>
Specifies the VCD file you want to use for post-processing.
-fsdb
To dump an fsdb file
-xman=4:combines All source files to a single file 'TOKENS.V'
E.g:vcs ADD4.V top.v-xman=4
-L filename:specifies a file where VCS records compilation messages. If You
Also enter The-r option, vcsrecords messages from both
Compilation and simulation in the same file.
2, Fsdbdumpfile and fsdbdumpvars to dump an fsdb file.
fsdbdumpfile -Specify FSDB file name
-Syntax: $fsdbDumpfile ('FSDB name')
-Function: Save the dump data into a designated file
fsdbdumpvars -Dump specified variable
-Grammar: $fsdbDumpvars; $fsdbDumpvars (Leval,module/var);
-function: Dump the variable you want to observe and store it in the Fsdb file.
$fsdbDumpon, $fsdbDumpfileoff
-function: Turn on/off dump variable function
$fsdbDumpMem, $fsdbDumpMenNow
-Syntax: $fsdbDumpMem, $fsdbDumpMemNow
-Function: Store the memory value to Fsdb file, when the call $fsdbdumpmemnow the memory value will be immediately dump out, and the call $fsdbdumpmem must wait until the end of the time interval to dump out.
Example 1:
Example 2:
Note: Example 1 and Example 2 have all the signal waveforms in the router_test_io and test two modules in the Test.sfdb file.
3. Execute SIMV (binary test file used by VCs generation emulation) file
Command:./SIMV [Run_time_options]
Run_time_options
Synopsys Vcs 2019 Crack
-s:stops Simulation at time 0
E.g:./simv-s
4. Interactive mode (interactive)
Allows real-time control simulations to be performed, allowing changes to register values or settings during simulation, which can affect simulation results in real time
5. post-processing mode (background processing mode)
The signal of the user-specified selection is first exported to a file, and then the file can be analyzed using Virsim. The file is of type vcd+, and the vcd+ file is a binary format that records information such as the results of VCs simulations, and the history of signal changes.
6, VCs compiler attention issues:
When using VCS compilation, you must first put a document containing ' timescale or macro definitions in front of you, or you will report an error
ERROR-[ITSFM] illegal ' timescale for module
ROUTER_TEST_TOP.SV, 7
Module 'Router_test_top' have ' timescale but previous module (s)/package (s) does
Not.
Please refer LRM 1364-2001 section 19.8.
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